libpfm_intel_adl_glc(3) — Linux manual page

NAME \| SYNOPSIS \| DESCRIPTION \| MODIFIERS \| FRONTEND_RETIRED event \| OFFCORE_RESPONSE events \| AUTHORS \| COLOPHON

LIBPFM(3)               Linux Programmer's Manual              LIBPFM(3)

NAME top

       libpfm_intel_adl_glc - support for Intel Alderlake Goldencove (P-
       Core) core PMU

SYNOPSIS top

       #include <perfmon/pfmlib.h>

       PMU name: adl_glc
       PMU desc: Intel Alderlake Goldencove (P-core)

DESCRIPTION top

       The library supports the Intel Alderlake Goldencove (P-Core) core
       PMU. It should be noted that this PMU model only covers each
       core's PMU and not the socket level PMU.  Because the processor
       uses a hybrid architecture with a P-Core and E-Core with a
       different PMU model, it may be necessary to force a PMU instance
       name to get the desired encoding. For instance, to encode for the
       P-Core adl_glc::BR_INST_RETIRED and for the E-core
       adl_grt::BR_INST_RETIRED.

       On Adlerlake Goldencove (P-Core), the number of generic counters
       depends on the Hyperthreading (HT) mode.

       The pfm_get_pmu_info() function returns the maximum number of
       generic counters in num_cntrs.

MODIFIERS top

       The following modifiers are supported on Intel SapphireRapid
       processors:

       u      Measure at user level which includes privilege levels 1,
              2, 3. This corresponds to PFM_PLM3.  This is a boolean
              modifier.

       k      Measure at kernel level which includes privilege level 0.
              This corresponds to PFM_PLM0.  This is a boolean modifier.

       i      Invert the meaning of the event. The counter will now
              count cycles in which the event is not occurring. This is
              a boolean modifier

       e      Enable edge detection, i.e., count only when there is a
              state transition from no occurrence of the event to at
              least one occurrence. This modifier must be combined with
              a counter mask modifier (m) with a value greater or equal
              to one.  This is a boolean modifier.

       c      Set the counter mask value. The mask acts as a threshold.
              The counter will count the number of cycles in which the
              number of occurrences of the event is greater or equal to
              the threshold. This is an integer modifier with values in
              the range [0:255].

       intx   Monitor the event only when executing inside a
              transactional memory region (in tx). Event does not count
              otherwise. This is a boolean modifiers. Default value is
              0.

       intxcp Do not count occurrences of the event when they are inside
              an aborted transactional memory region. This is a boolean
              modifier. Default value is 0.

       ldlat  Pass a latency threshold in core cycles to the
              MEM_TRANS_RETIRED:LOAD_LATENCY event.  This is an integer
              attribute that must be in the range [1:65535]. It is
              required for this event. The library provides a set of
              presets for specific latencies, such as 128.  Note that
              the event must be used with precise sampling (PEBS).

FRONTEND_RETIRED event top

       For Alderlake Goldencove (P-Core), the library uses the hardcoded
       bubble width and bubble length provided by Intel preset events.
       It is not possible to tweak either the latency or the width via
       the library.

OFFCORE_RESPONSE events top

       Intel Alderlake Goldencove (P-Core) supports two encodings for
       offcore_response events (0x2a, 0x2b). In the library, these are
       called OCR0 and OCR1. The two encodings are equivalent. On Linux,
       the kernel can schedule any OCR encoding into any of the two OCR
       counters.  The offcore_response events are exposed as a normal
       events by the library. The extra settings are exposed as regular
       umasks. The library takes care of encoding the events according
       to the underlying kernel interface.

       On Intel Alderlake Goldencove (P-Core), the event is treated as a
       regular event with a flat set of umasks to choose from.  It is
       not possible to combine the various requests, supplier, snoop
       bits anymore. The library offers the list of validated
       combinations as per Intel's official event list.

AUTHORS top

       Stephane Eranian <[email protected]>

COLOPHON top

       This page is part of the perfmon2 (a performance monitoring
       library) project.  Information about the project can be found at
       ⟨http://perfmon2.sourceforge.net/⟩.  If you have a bug report for
       this manual page, send it to
       [email protected].  This page was obtained
       from the project's upstream Git repository
       ⟨git://git.code.sf.net/p/perfmon2/libpfm4 perfmon2-libpfm4⟩ on
       2024-06-14.  (At that time, the date of the most recent commit
       that was found in the repository was 2024-04-24.)  If you
       discover any rendering problems in this HTML version of the page,
       or you believe there is a better or more up-to-date source for
       the page, or you have corrections or improvements to the
       information in this COLOPHON (which is not part of the original
       manual page), send a mail to [email protected]

                             February, 2024                    LIBPFM(3)